Today’s post is about the basics of VLSI. VLSI is the acronym of Very Large Scale Integration. In a VLSI chip, the number of transistors that are integrated ranges from 20,000-100,000. The type of transistors used is varied based on application. In this post and a couple of following posts, I will be writing about NMOS transistors and extending it to CMOS. Today, GaAs transistors are being used as they also have lower power consumption and are fast at the same time. Also, their design is on similar lines as that of NMOS. So basically, once you’re thorough with design of NMOS, everything else is pretty much just an extension.
Understanding the working of a MOS transistor is very important to understand VLSI, so I will begin with MOS. MOS is short for Metal Oxide Semiconductor. As the name suggests, these transistors are, in general sense a combination of metal and silicon oxide. (Today, polysilicon is used instead of the metal, but the name still remains MOS) Most importantly, these are Field Effect Transistors (FETs), which means, they work based on the variations of the voltage supplied to them and not on the variations of current supplied to them. This difference has to be understood because that’s what differentiates BJTs (which are now obsolete) and FETs.
Basically any FET contains three terminals, Drain, Gate and Source(4th also exists, called the bulk terminal. To put it simply though, 3 terminals maybe studied). The output current is produced between source and drain, with the voltage supplied to the gate. (This sentence may be hard to follow for laymen, but just go with me on this one; explanation is on its way) When I say output flows between source & drain, it means that there’s a path for it flow and that path is called the “channel”.
Based on whether the channel is present or absent when the transistor is idle, a MOS transistor is classified as:
1. Depletion-MOS (DMOS): Where the channel is present when the MOS is idle.
2. Enhancement-MOS (EMOS): Where the channel is absent when the MOS is idle.
These classifications basically give an idea if the transistor is ON or OFF, when idle (i.e. when there is no voltage input on the gate terminal). So, since a channel exists on the DMOS, this transistor is ON even when there is no voltage at the gate. And the EMOS is OFF, when there is no voltage supplied at the gate. Each of them has separate applications.
The first image is the basic MOS symbol and the second one is cross sectional view of an n-channel MOSFET. Commonly, the EMOSFET is used in the construction of CMOS.
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| credits: www.elprocus.com |
The Depletion MOSFET:
This transistor conducts even when gate-source voltage is zero (i.e. Vgs = 0). Consider a positive voltage across drain-source (i.e. Vds =0). Then, positive voltage at the drain attracts electrons in the channel. This motion of electrons cause the drain current Ids. Hence, the depletion MOSFET conducts at zero gate-source voltage.
Generally, there is a particular threshold gate-source voltage above which only, a MOSFET begins to conduct. In case of n channel DMOS this voltage is negative (because the transistor conducts even at zero gate-source voltage).
The Enhancement MOSFET:
I will explain this in detail. Here, we need an above-zero threshold voltage for the transistor to conduct (because the channel needs to be established, it is not present by default like in DMOS).
There are three cases in the working of these devices:
1. Vgs>Vt but Vds=0 (Cutoff region): Here, the voltage at the gate is positive with respect to the source. So, the holes (substrate is p-type) start to repel from the region right below the gate. This means that the particular region is depleted of holes. Now if the Vgs is sufficiently large, it starts to attract electrons towards the region which is now depleted of holes. This establishes the n-channel (which is also called inversion region) and the depletion region is pushed below that region.
2. Vgs > Vt and Vds=0 but Vg>Vd (Linear region): The channel is established and now, electrons begin to flow from source to drain due to positive Vds. At the source end, Vg is the controlling voltage, but at the drain end, Vg-Vd is the controlling voltage. This particular condition is called the linear condition where, the current is dependent on both Vgs and Vds. The channel is resistive.
3. Vgs > Vt but Vg<Vd (Saturation Region): In this case, the effective voltage at drain becomes less than the threshold voltage required for the channel to be established and that’s why the channel is pinched off before it reaches the drain. Now, the channel becomes highly resistive; but since the drain voltage is high, it still attracts the electrons. So the electrons continue to conduct (from drift mechanism) and they jump to the depletion region and get accelerated towards the drain. This particular condition is called saturation condition. So, now the channel current is almost fully independent of the drain voltage and is dependent only on the Vgs. So the transistor in this condition can act as a stable current source.
In the first condition we see the important difference between a BJT and FET. i.e. in the pn junction of BJT, electrons are introduced because of donor atoms, but in FET, electrons are introduced due to the gate voltage. Hence, an FET acts as a voltage controlled device; controlling voltage is the gate-source voltage.
I have written only about the n-channel MOSFET, but the p-channel MOSFET is its dual. Hence, to conduct, a p-channel MOS needs negative gate-source voltage. Every other mechanism remains the same. Also, mobility of holes is lower than that of electrons.
Here are some links to further explanation and videos:
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